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Primary Examiner: Rutledge, L. Dewayne
Assistant Examiner: Saba, W. G.
Attorney: Fleit & Jacobson

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Title: Method for manufacturing electrical solid state devices utilizing shadow masking and ion-implantation

Abstract: The present invention describes the manufacture of a chip having a stratum in which a number of diffusions are spaced from each other by boundaries whose widths is the width of a gap. The diffusion on one side of a boundary is formed by ion bombardment, and that on the other side by heat transfer of ions of a material with which the film has been doped.


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Inventors: Godber, Geoffrey Allan (Long Buckby, EN)

Application Number: 726796
Filing Date: 1976-09-27
Publication_date: 1978-04-18
Assignee: Plessey Handel und Investments A.G. (Zug, CH)
Primary Class(es): 438/531 216/48, 216/66, 257/368, 257/E21.033, 257/E21.151, 257/E21.346, 438/372, 438/535
Other Classes:
US Patent Ref:
3523042Aug, 1970Bower et al.148/1.
3537925Nov, 1970Chen156/659.
3676230Jul, 1972Rice148/188.
3758943Sep, 1973Shibata29/579.
3866310Feb, 1975Driver et al.29/579.
3940288Feb, 1976Takagi et al.148/1.
3964156Jun, 1976Williams et al.29/579.
3972756Aug, 1976Nagase et al.148/187.
3980508Sep, 1976Takamiya et al.148/188.

Other Refs: 1,388,535
Mar, 1975UK.
Other References: Carlsen, G.S., "Multiple Division for Integrated . . . Diffusion", I.B.M. Tech. Discl. Bull., vol. 9, No. 10, Mar. 1967, pp. 1456-1457.