Title: Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control

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Abstract: An associative system for providing virtual paged stores with on-chip associative address translation and control functions. Each of a plurality of integrated circuit chips contains the storage cells for a unit of data and at least one associative circuit including a virtual page address register for storing the virtual address bits assigned to each page. The CPU includes a virtual page address register and a real address register, with the CPU virtual page address register being connected to the virtual address register on each chip for interrogating the chips when a page request is made. The real address register holds the real address bits for selecting a byte of data from the chips. An interrogate virtual page address is applied to each of the chips for comparison with the address stored in the virtual page address registers, whereby a match will directly enable the selected chip to be read and/or written into. In addition to the virtual page address translation performed directly on the chip, there may also be provided on each chip a page usage information register, a page update register, as well as other control registers for storing page data which is used to determine eligibility of a page for replacement when a page fault is detected.


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