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Title:
Method of fabricating semiconductor device
Abstract:
An improved method for forming an isolation region of electrical insulator between elements of a semiconductor device, comprising depositing an electrical insulator at a low temperature to cover one major surface of a semiconductor substrate and to fill a groove provided in this surface of the semiconductor substrate, coating the electrical insulator layer with another electrical insulator which is etched at a rate approximately equivalent to that of the former electrical insulator, so as to make the entire top surface of the electrical insulator layer parallel to the major surface of the substrate, and then applying physical etching using ions to remove the electrical insulator layers until the surface of the substrate is exposed, whereby to provide in the groove an isolation region having a satisfactory surface flatness.
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Inventors:
Kaji, Tadao (Tokyo, JA) Homma, Yoshio (Hachioji, JA)
Application Number:
714197
Filing Date: 1976-08-13 Publication_date: 1978-02-14 Assignee:
Hitachi, Ltd. (JA)
Primary Class(es):
438/359
148/DIG50, 148/DIG51, 148/DIG85, 148/DIG118, 204/192.32, 257/517, 257/586, 257/E21.245, 257/E21.25, 257/E21.549, 257/E29.018, 438/424, 438/702
Other Classes:
US Patent Ref:
Other Refs:
Other References:
IBM Technical Disclosure Bulletin, "Double Poly-Silicon Isolation for IC", by Doo, vol. 8, No. 5, Oct. 1965, pp. 802 and 803. |