Title: Microprocessor with parallel operation

Abstract: A highly parallel microprocessor using a logic gating structure and a microinstruction organization which permits direct access by each of the microprocessor components to a tri-bus system. Operation is defined by a single phase clock, during which all portions of a microinstruction are executed. The system further permits overlap operation for microprocessor instructions, thereby allowing for the fetching of a next instruction while executing a current instruction. The use of general purpose, non-dedicated registers is contemplated, thereby to avoid the need for multi-phase clocking.

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Inventors: Garlic, Richard A. (Irvine, CA, US)

Application Number: 625627
Filing Date: 1975-10-24
Publication_date: 1977-09-20
Assignee: Xerox Corporation (Stamford, CT)
Primary Class(es): 712/42
Other Classes:
US Patent Ref:

3374466	Mar, 1968	Hane et al.	340/172.
3673575	Jun, 1972	Burton	340/172.
3675214	Jul, 1972	Ellis	340/172.
3702988	Nov, 1972	Haney	340/172.
3725868	Apr, 1973	Malme, Jr. et al.	340/172.
3748649	Jul, 1973	McEowen	340/172.
3798615	Mar, 1974	Weisbecker	340/172.
3909790	Sep, 1975	Shapiro et al.	340/172.
3938098	Feb, 1976	Garlic	340/172.

Other Refs:
Primary Examiner: Springborn, Harvey E.
Assistant Examiner:
Attorney: Ralabate; James J., Weiss; Franklyn C., Taylor; Ronald L.