Title: CPU - I/O bus interface for a data processing system

Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device ransceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.

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Inventors: Hendrie, Gardner Cox (Carlisle, MA, US)
Crafts, Harold Springer (Saratoga, CA, US)

Application Number: 662180
Filing Date: 1976-02-27
Publication_date: 1977-09-13
Assignee: Data General Corporation (Westboro, MA)
Primary Class(es): 710/305
Other Classes:
US Patent Ref:

3742456	Jun, 1973	McFiggans et al.	340/172.
3863226	Jan, 1975	Ryburn	340/172.

Other Refs:
Primary Examiner: Zache, Raulfe B.
Assistant Examiner:
Attorney: Wall; Joel, Frank; Jacob