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Title: Method of making a junction type field effect transistor

Abstract: In the manufacture of a vertical structure junction type field effect transistor, the formation of a gate region is followed by an oxidation treatment of the upper surface of the gate region and then by the growth of a semiconductor layer consisting of a monocrystalline region on the channel portion and a polycrystalline region on the oxide film formed on the gate region. The existence of the oxide film on the gate region prevents the out-diffusion of the impurity doped in the gate region, preventing the lowering of the breakdown voltage, and enabling a short channel length and small series resistance of the channel.


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Inventors: Kobayashi, Sadao (Hachioji, JA)

Application Number: 683265
Filing Date: 1976-05-05
Publication_date: 1977-07-19
Assignee: Hitachi, Ltd. (JA)
Primary Class(es): 438/192 148/DIG88, 257/264, 257/266, 257/E21.131, 257/E29.003, 257/E29.313, 438/193, 438/969
Other Classes:
US Patent Ref:
3497777Feb, 1970Teszner357/22.
3617826Nov, 1971Kobayashi357/22.
3619737Nov, 1971Chiu357/22.
3648128Mar, 1972Kobayashi148/175.
3653120Apr, 1972Sirrine et al.148/174.
3681668Aug, 1972Kubayashi357/22.
3725751Apr, 1973Wakamiya148/175.
3814995Jun, 1974Teszner357/22.
3977017Aug, 1976Ishitani357/22.

Other Refs:
Primary Examiner: Rutledge, L. Dewayne
Assistant Examiner: Saba, W. G.
Attorney: Craig & Antonelli