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Title:
Method of making a junction type field effect transistor
Abstract:
In the manufacture of a vertical structure junction type field effect transistor, the formation of a gate region is followed by an oxidation treatment of the upper surface of the gate region and then by the growth of a semiconductor layer consisting of a monocrystalline region on the channel portion and a polycrystalline region on the oxide film formed on the gate region. The existence of the oxide film on the gate region prevents the out-diffusion of the impurity doped in the gate region, preventing the lowering of the breakdown voltage, and enabling a short channel length and small series resistance of the channel.
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Inventors:
Kobayashi, Sadao (Hachioji, JA)
Application Number:
683265
Filing Date: 1976-05-05 Publication_date: 1977-07-19 Assignee:
Hitachi, Ltd. (JA)
Primary Class(es):
438/192
148/DIG88, 257/264, 257/266, 257/E21.131, 257/E29.003, 257/E29.313, 438/193, 438/969
Other Classes:
US Patent Ref:
Other Refs:
Primary Examiner:
Rutledge, L. Dewayne
Assistant Examiner:
Saba, W. G.
Attorney:
Craig & Antonelli
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