Title: High density/high speed MOS process and device

Abstract: A process for fabricating MOS silicon gate transistors which provide high density and high speed devices. The process includes the use of a boron ion implantation step to prevent punch-through and to adjust the thresholds of enhancement mode transistors. Both enhancement mode and depletion mode transistors are simultaneously produced with the disclosed process.

Do you think this is a good invention? Vote now:

Votes so far: For:(0) Against:(0)
Other info:

Inventors: Pashley, Richard D. (Mountain View, CA, US)

Application Number: 641259
Filing Date: 1975-12-16
Publication_date: 1977-07-05
Assignee: Intel Corporation (Santa Clara, CA)
Primary Class(es): 438/276 257/392, 257/E21.336, 257/E21.337, 257/E21.433, 257/E21.538, 257/E21.544, 257/E21.616, 257/E27.061, 438/280, 438/281
Other Classes:
US Patent Ref:

3646665	Mar, 1972	Kim	357/42.
3660735	May, 1972	McDougall	357/42.
3752711	Aug, 1973	Kooi	29/571.

Other Refs:
Primary Examiner: Tupman, W.
Assistant Examiner:
Attorney: Blakely, Sokoloff, Taylor & Zafman