Title: High-frequency CCD adder and multiplier

Abstract: A device for implementing the arithmetic operations of addition and multication utilizing CCD concepts and MOSFET properties. First and second CCD channels convert first and second input voltages into first and second charge quantities, respectively. The first and second charge quantities are added in a third CCD channel to provide a third charge quantity linearly proportional to the sum of the first and second input voltages. The three charge quantities are sensed by three floating gate amplifiers operated in the saturation region. The outputs of the floating gate amplifiers are subsequently combined by a differential amplifier, the output of which is linearly proportional to the product of the first and second input voltages.

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Inventors: Lagnado, Isaac (San Diego, CA, US)

Application Number: 661689
Filing Date: 1976-02-26
Publication_date: 1977-06-28
Assignee: The United States of America as represented by the Secretary of the Navy (Washington, DC)
Primary Class(es): 708/835 257/236, 257/239, 377/47
Other Classes:
US Patent Ref:

3809923	May, 1974	Esser	307/221.
3931510	Jan, 1976	Kmetz	235/193.
3935439	Jan, 1976	Buss et al.	307/221.
3952188	Apr, 1976	Sloate et al.	235/193.
3956624	May, 1976	Audaire et al.	235/193.

Other Refs:
Primary Examiner: Ruggiero, Joseph F.
Assistant Examiner:
Attorney: Sciascia; R. S., Rubens; G. J., Fendelman; H.