Title: Gate input circuit for insulated gate field effect transistors

Abstract: In a gate input circuit for insulated gate field effect transistors, an insulated gate field effect transistor of depletion type is used, whose drain electrode (or source electrode) is connected to one terminal of a power source and whose source electrode (or drain electrode) is short-circuited with the gate electrode and connected to an input terminal of the gate input circuit through a resistor.

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Inventors: Shimada, Shunji (Kodaira, JA)
Ohba, Kenichi (Fuchu, JA)
Ishii, Shigeo (Tokyo, JA)

Application Number: 658922
Filing Date: 1976-02-18
Publication_date: 1977-03-08
Assignee: Hitachi, Ltd. (JA)
Primary Class(es): 327/389 327/434, 327/581, 361/54, 361/88
Other Classes:
US Patent Ref:

3395290	Jul, 1968	Farina et al.	307/205.
3555374	Jan, 1971	Usuda	307/304.
3588525	Jun, 1971	Hatsukano et al.	307/304.
3636385	Jan, 1972	Koepp	307/304.
3934159	Jan, 1976	Nomiya et al.	307/304.
3947727	Mar, 1976	Stewart	317/31.

Other Refs:
Primary Examiner: Heyman, John S.
Assistant Examiner: Anagnos, Larry N.
Attorney: Craig & Antonelli