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Title:
MOSFET detecting and synchronizing circuit for asynchronous digital data
Abstract:
An asynchronous data input signal is detected and synchronized by a fast-acting circuit. The input is used to modulate a local clock and a detecting latch is then driven by the data-modulated clock. Most of the propagation delay found in conventional detector-synchronizers is eliminated since the SET input to the latch, which is essentially the clock signal, is generated without any gate delay and the CLEAR input is generated with only a single gate delay. Thus, the circuit is well suited for multiple clock systems in which detection and synchronization to one clock must be accomplished before the pulse of a second clock begins.
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Inventors:
Alvarez, Jr., Cesar E. (Griffith, IN, US)
Application Number:
609265
Filing Date: 1975-09-02 Publication_date: 1977-03-08 Assignee:
Teletype Corporation (Skokie, IL)
Primary Class(es):
327/141
327/155, 327/162, 327/299
Other Classes:
US Patent Ref:
Other Refs:
Other References:
"Low Power Gated FET Latch" by Kraft et al in IBM Tech. Discl. Bull., vol. 15, No. 7, Dec. 1972, p. 2280. |