Title: FET load gate compensator

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Abstract: An FET load gate compensator employing feedback to control the load gate voltage holds the circuit delay and power dissipation of an integrated circuit nearly constant. The integrated circuit chip is provided with several stages of inverters which act as a delay sensor to simulate the delay of the operational circuit on the chip. The time delay of the delay sensor on the integrated circuit chip is compared with an external clock reference by a delay comparator. The delay comparator generates an output voltage which is used to adjust the load gate voltage until the delay in the delay sensor is equal to the clock reference. Since the same load gate voltage is distributed in the rest of the operational circuits in the integrated circuit chip, the delay times of these circuits will track with that of the delay sensor and thus also tend to be held constant.


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