Title: Self-zeroing analog-to-digital conversion system

Abstract: A self-zeroing, drift-free analog-to-digital conversion system is disclosed in which a single amplifier is shared between an analog-to-digital converter circuit and a sample-and-hold circuit. The offset errors generated by the sample-and-hold circuit cancel with the offset errors generated by the analog-to-digital converter circuit since the circuitry introducing the offset errors is shared. As a result, system offset errors are negated and the system enables changing from a unipolar to bipolar input range without inclusion of any additional circuitry. Usage of a gain preamplifier is provided with no corresponding system offset errors being introduced. moreover, usage of a differential-input gain preamplifier is also provided, with the self-zeroing feature resulting in greatly improved common-mode rejection.

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Other info:

Inventors: Lipcon, Jesse B. (Brighton, MA, US)

Application Number: 498500
Filing Date: 1974-08-19
Publication_date: 1976-09-21
Assignee: Digital Equipment Corporation (Maynard, MA)
Primary Class(es): 341/118 327/96, 341/165
Other Classes:
US Patent Ref:

3516002	Jun, 1970	Hillis	340/347.
3653037	Mar, 1972	Utley	340/347.
3706986	Dec, 1972	Petit	340/347.
3736586	May, 1973	Donjon	340/347.

Other Refs:
Primary Examiner: Miller, Charles D.
Assistant Examiner:
Attorney: Gunther; John M., Siekman; Thomas C.