Title: Computer control apparatus

Abstract: The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction with certain bits from a storage data register (SDR) concatenated with certain bits from an operand register to form the branch to address in SAR. The instruction counter is incremented in the usual manner but the incremented address is not loaded into SAR. The clock is advanced to the second rather than the first time state of the next instruction fetch cycle. Thereafter, the branch to address which is residing in the operand register, is incremented and loaded into the instruction counter.

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Inventors: Bodner, Ronald E. (Rochester, MN, US)
Crooks, Thomas L. (Rochester, MN, US)
Magrisso, Israel B. (Coral Springs, FL, US)
Slack, Keith M. (Rochester, MN, US)
Smith, Richard S. (Boca Raton, FL, US)

Application Number: 529677
Filing Date: 1974-12-04
Publication_date: 1976-06-01
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Class(es): 712/234 711/213
Other Classes:
US Patent Ref:

3417379	Dec, 1968	Heard et al.	340/172.
3656123	Apr, 1972	Carnevale et al.	340/172.

Other Refs:
Primary Examiner: Shaw, Gareth D.
Assistant Examiner: Bartz, C. T.
Attorney: Voss; Donald F.