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Title:
Fixed point to floating point conversion in an electronic computer
Abstract:
In a digital electronic computer which comprises a memory including a first and a second register, the first register is receptive of a number to be converted from fixed to floating point notation and the second register is receptive of a significant zero digit with an associated decimal point. Shifting means including a register is operable to shift the contents of either register and aligning means is operable to cause shifting of the second register until the decimal point stored therein is aligned with the decimal point in the first register. Indicating means indicates whether the number stored in the first register is greater or less than one and the shifting means next begins shifting the contents of one or the other of the registers when the number is indicated greater or less than one respectively. A control means includes a detecting means for stopping the shifting means when the decimal point of the second register becomes aligned with the location of the next higher order with respect to the highest significant digit of the first register. The control means also includes counting means which is incremented or decremented by one for each shifting operation in dependence on the direction of shifting. The resultant numbers in the first and and second registers represent the mantissa and exponent respectively, of the desired floating point number.
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Inventors:
De Sandre, Giovanni (Brugherio (Milan), IT) Subrizi, Angelo (Ivrea (Turin), IT) Bretti, Franco (Are' Di Caluso (Turin), IT)
Application Number:
461558
Filing Date: 1974-04-17 Publication_date: 1976-06-01 Assignee:
Ing. C. Olivetti & C., S.p.A. (Ivrea (Turin), IT)
Primary Class(es):
341/75
Other Classes:
US Patent Ref:
Other Refs:
Primary Examiner:
Shaw, Gareth D.
Assistant Examiner:
Sachs, Michael C.
Attorney:
Schaefer; I. J.
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