Title: Phase locked loop lock detector and method

Abstract: Apparatus and method for determining when a phase lock loop is in a state of lock is disclosed. The input frequency and the VCO frequency of a phase locked loop are combined by a difference multiplier to produce a signal having their difference frequency. The difference frequency signal is transformed into a squarewave by a limiter and the squarewave is then fed into a binary counter which counts the frequency of the squarewave pulses. Circuitry including a clock, two monostables, an AND gate, and a one cycle memory flip-flop periodically monitors the count of the binary counter and produces a signal indicating a state of unlock when the count of the binary counter exceeds a predetermined limit. An inhibit signal which prevents the binary counter from continuing to count is generated when the predetermined count limit has been reached in any one monitored time period.

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Other info:

Inventors: Seitz, Martin V. (Fox River Grove, IL, US)
Hennen, Harry A. (Bloomingdale, IL, US)

Application Number: 525521
Filing Date: 1974-11-20
Publication_date: 1976-05-11
Assignee: Motorola, Inc. (Chicago, IL)
Primary Class(es): 331/1A 327/3, 327/43, 327/241, 331/11, 331/17, 331/25, 331/DIG2
Other Classes:
US Patent Ref:

3185938	May, 1965	Pelosi	331/11.
3401353	Sep, 1968	Hughes	331/18.
3611175	Oct, 1971	Boelke	331/17.
3694766	Sep, 1972	Boelke	331/25.

Other Refs:
Primary Examiner: Grimm, Siegfried H.
Assistant Examiner:
Attorney: Gillman; James W., Parsons; Eugene A.