Title: D. C. Stable semiconductor memory cell

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

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Inventors: Askin, Haluk O. (Stanfordville, NY, US)
Jacobson, Edward C. (Poughkeepsie, NY, US)
Lee, James M. (Poughkeepsie, NY, US)
Sonoda, George (Poughkeepsie, NY, US)

Application Number: 535875
Filing Date: 1974-12-23
Publication_date: 1976-04-06
Assignee: IBM Corporation (Armonk, NY)
Primary Class(es): 365/203 365/154, 365/190
Other Classes:
US Patent Ref:

3157859	Nov, 1964	Moore et al.	340/173.
3161858	Dec, 1964	Sanders et al.	340/173.
3535699	Oct, 1970	Gaensslen et al.	340/173.
3576571	Apr, 1971	Booher	340/173.
3806898	Apr, 1974	Askin	340/173.
3836894	Sep, 1974	Cricchi	340/173.
3868656	Feb, 1975	Stein et al.	340/173.

Other Refs:
Primary Examiner: Canney, Vincent P.
Assistant Examiner:
Attorney: Galanthay; T. E.