Title: Self-aligned method for integrated circuit manufacture

Abstract: A method for manufacturing integrated circuits provides total self-alignment of all critically positioned device regions. Self-alignment is accomplished by a combination of selectively etchable thin layers on the surface of a semiconductor body. An initially formed predetermined pattern of openings defines all active regions of the device. Selective introduction of impurities in sub-sets of this predetermined pattern form regions of a semiconductor device in a totally self-aligned manner while ion implantation through all overlying layers provides for the formation of further shallow device regions irrespective of the predetermined pattern of openings.

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Inventors: Mills, III, B. David (Tempe, AZ, US)

Application Number: 572971
Filing Date: 1975-04-30
Publication_date: 1976-04-06
Assignee: Motorola, Inc. (Chicago, IL)
Primary Class(es): 438/370 148/DIG43, 148/DIG85, 148/DIG106, 257/593, 257/E21.552, 257/E21.608, 438/350, 438/357
Other Classes:
US Patent Ref:

3595716	Jul, 1971	Kerr et al.	148/187.
3704177	Nov, 1972	Beale	148/1.
3783047	Jan, 1974	Paffen et al.	148/187.
3789504	Feb, 1974	Jaddam	148/187.
3793088	Feb, 1974	Eckto, Jr.	148/1.

Other Refs:
Primary Examiner: Rutledge, L. Dewayne
Assistant Examiner: Davis, J. M.
Attorney: Weiss; Harry M., Stevens; Kenneth R.