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Title:
Two part package for a semiconductor die
Abstract:
Semiconductor devices containing integrated circuits are attached directly to external package leads by pressing simultaneously a plurality of groups of leads against bonding pads on a plurality of face-up semiconductor dice and heating the composite structures. Solder bumps on the bonding pads contain hard pedestals which prevent the overlying leads from being pushed into the faces of the semiconductor devices while the solder on the solder bumps melts to form the bonds between the leads and the underlying semiconductor dice. The process for carrying out this operation lowers significantly the cost of each packaged semiconductor device and the resulting structure is more reliable than structures of the prior art.
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Inventors:
Duffek, Edward F. (Cupertino, CA, US) Funk, Ernest J. (Cupertino, CA, US) Jankowski, Alfred S. (San Jose, CA, US) Lane, Jack C. (Saratoga, CA, US) Lehner, William L. (Los Altos Hills, CA, US) Oliver, Floyd F. (Los Altos, CA, US) Schneider, Mark R. (San Jose, CA, US)
Application Number:
099904
Filing Date: 1970-12-21 Publication_date: 1976-03-30 Assignee:
Signetics Corporation (Sunnyvale, CA)
Primary Class(es):
257/669
257/672, 257/738, 257/E23.021, 257/E23.043, 257/E23.047, 257/E23.055
Other Classes:
US Patent Ref:
Other Refs:
Primary Examiner:
Edlow, Martin H.
Assistant Examiner:
Wojciechowicz, E.
Attorney:
Flehr, Hohbach, Test, Albritton & Herbert
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