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Title:
Method for fabricating double-diffused, lateral transistors
Abstract:
A double-diffused, lateral transistor structure is fabricated utilizing an etch resistant mask to provide self-aligning positional accuracy for formation of active areas of the transistor. The lateral structure includes semiconductor material having at least one substantially flat surface, and the structure includes at least one region of insulating material formed adjacent the flat surface, the top surface of the insulating material being substantially coplanar with said one surface. A collector is formed in the semiconductor material adjacent first portions of both the flat surface and the insulating material, while an emitter is formed in the semiconductor material adjacent second portions of both the flat surface and the insulating material. A base separates the collector from the emitter.
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Inventors:
Schinella, Richard D. (Mountain View, CA, US) Anthony, Michael P. (San Carlos, CA, US)
Application Number:
570124
Filing Date: 1975-04-21 Publication_date: 1976-03-23 Assignee:
Fairchild Camera and Instrument Corporation (Mountain View, CA)
Primary Class(es):
438/339
148/DIG53, 148/DIG96, 148/DIG106, 148/DIG167, 257/575, 257/E21.553, 257/E21.609, 257/E27.054, 438/377, 438/492, 438/546
Other Classes:
US Patent Ref:
Other Refs:
Other References:
zeidenbergs, G., "Lateral PNP . . . Collector," I.B.M. Tech. Discl. Bull., Vol. 14, No. 11, Apr. 1972, p. 3248. |