Title: Process for the fabrication of silicon transistors with high DC current gain

Abstract: A monocrystalline silicon wafer is prepared which has formed therein the usual emitter, base and collector regions. A groove is then formed to a predetermined depth in the top surface of the silicon wafer so as to extend along the P-N junction between the base and emitter regions. A silicon oxide layer is formed over the wafer, as by heating the same in an oxidative atmosphere, and the wafer is succeedingly heated in a hydrogenous atmosphere. The silicon oxide layer may be selectively photoetched away where the electrodes are to be formed for the emitter, base and collector of the transistor.

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Inventors: Yoshizawa, Yutaka (Niiza, JA)

Application Number: 546126
Filing Date: 1975-01-31
Publication_date: 1976-03-09
Assignee: Sanken Electric Company Limited (JA)
Primary Class(es): 438/350 148/33.5, 148/DIG36, 148/DIG49, 148/DIG51, 148/DIG85, 257/586, 257/E21.212, 257/E21.241, 438/376, 438/546
Other Classes:
US Patent Ref:

3426253	Feb, 1969	Roque et al.	357/34.
3772577	Nov, 1973	Planey	357/34.
3858234	Dec, 1974	Olson	357/34.

Other Refs:
Primary Examiner: Rutledge, L. Dewayne
Assistant Examiner: Davis, J. M.
Attorney: Woodcock, Washburn, Kurtz & Mackiewicz