Title: Data processing unit having a plurality of hardware circuits for processing data at different priority levels

Abstract: A data processing unit having a plurality of hardware data processing circuits each one including a program counter register for addressing the microinstructions, an accumulator register and an addressing register for storing the addressing of the operands of the microinstructions. Means are provided for switching the CPU from the hardware data processing circuits having a predetermined priority level to the hardware data processing circuits having a less priority level, by executing a particular microinstruction, which includes information either about the changing of the priority level or about the memory address of the starting microinstruction of the microprogram to be executed on the less priority level.

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Inventors: Sajeva, Raoul (Turin, IT)

Application Number: 464726
Filing Date: 1974-04-26
Publication_date: 1976-02-24
Assignee: Ing. C. Olivetti & C., S.p.A. (Ivrea, Turin, IT)
Primary Class(es): 710/244
Other Classes:
US Patent Ref:

3333252

Jul, 1967

Shimabukuro

340/172.

Other Refs:
Primary Examiner: Shaw, Gareth D.
Assistant Examiner: Thomas, James D.
Attorney: Schaefer; I. J.