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Primary Examiner: Jackmon, Edith Simmons
Assistant Examiner:
Attorney: Blum, Moscovitz, Friedman & Kaplan

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Title: Electronic timepiece semiconductor intergrated circuit

Abstract: A semiconductor integrated circuit especially suitable for use in electronic timepieces to improve the operation thereof is provided. An integrated circuit chip including complementary coupled P-channel and N-channel MOS field effect transistors having insulation placed therebetween by forming same spaced on an insulating substrate. The insulation effects reduced current consumption to thereby enhance the life of the battery in an electronic timepiece.

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Inventors: Morozumi, Shinji (Nagano, JA)

Application Number: 429992
Filing Date: 1974-01-02
Publication_date: 1976-02-24
Assignee: Kabushiki Kaisha Suwa Seikosha (Tokyo, JA)
Primary Class(es): 368/87 257/350, 257/E27.062, 257/E27.111, 327/581, 331/116FE, 968/823, 968/902, 968/DIG1
Other Classes:
US Patent Ref:

3585527	Jun, 1971	Luscher	331/116.
3715604	Feb, 1973	Rapshy	307/22.
3757510	Sep, 1973	Dill	58/50.

Other Refs: Other References: J. D. Wilcock, Most Digital Logic Circuits in Silicon Films Deposited, Sapphire Substrates, Solid-State Electronics, 1971, Vol. 14, pp. 315-325.
H. W. Kaiser et al., Recent Developments in CMOS/SOS, RCA Engineer, 8-1972, pp. 68-72.