Title: Signal generator comprising an addressable memory

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Abstract: A circuit for and a method of utilizing an addressable memory as the generator of timing pulse signals is disclosed. The memory has n separate input terminals for receiving the n-bits of an n-bit address word to address one of the 2.sup.n addressable registers therein. Each register stores an n-bit data word, and, when addressed, couples the n bits of the addressed data word to a separate associated one of n separate output terminals. N separate feedback conductors couple each separate one of the n output terminals back to only a separate associated one of the n input terminals. The memory, when enabled, reads out the data word stored in a first addressed one of its registers for continuously cycling the memory through its 2.sup.n registers by using the read out data word as the address word to address the next addressed register at the next memory cycle. N separate output signal conductors are coupled to each separate one of the n separate output terminals for providing, on each separate one of the n output signal conductors, n timing pulse signals.


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