Title: Method of manufacturing semiconductor devices

Abstract: A method of manufacturing semiconductor devices comprising a semiconductor element having a PN junction in which an N.sup.+-type region is formed in an N-type region constituting the PN junction and another N-type region is formed around the N.sup.+-type region and a metal layer is provided on the other N-type region and the N.sup.+-type region, thereby providing a mechanically and electrically improved ohmic contact to the semiconductor element.

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Inventors: Sugiyama, Masayoshi (Hitachi, JA)

Application Number: 537962
Filing Date: 1975-01-02
Publication_date: 1976-01-27
Assignee: Hitachi, Ltd. (JA)
Primary Class(es): 438/464 438/542
Other Classes:
US Patent Ref:

380805	Apr, 1974	Henning	29/583.
3343255	Sep, 1967	Donovan	29/590.
3360696	Dec, 1967	Neilson	357/89.
3542266	Nov, 1970	Woelfle	29/583.
3608186	Sep, 1971	Hutson	29/583.

Other Refs:
Primary Examiner: Tupman, W.
Assistant Examiner:
Attorney: Craig & Antonelli