Title: Bus controller for digital computer system

Abstract: An arrangement is shown for controlling transmission of blocks of information to and from a plurality of major components of a digital computer system interconnected by common buses. The disclosed arrangement operates so that any component of the system may normally seize, on a nonpriority basis, one of the buses at the beginning of any time slot defined by two successive clock pulses generated by a single source and applied to all components simultaneously; however, if a special instruction is encountered during execution of a program, any component may retain a bus for more than one time slot. The disclosed arrangement also permits error checking of transmitted information from a given major component without interfering with transmission from any other major component and automatically causes retransmission of any block of information found to be improperly transmitted originally. Still further, the disclosed arrangement permits buses to be dedicated during execution of a program or, if desired, any complete major component to be replaced without affecting any other major component.

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Other info:

Inventors: Deerfield, Alan J. (Newtonville, MA, US)
Nissen, Stanley M. (Reading, MA, US)

Application Number: 409846
Filing Date: 1973-10-26
Publication_date: 1976-01-13
Assignee: Raytheon Company (Lexington, MA)
Primary Class(es): 710/107 370/503, 714/748
Other Classes:
US Patent Ref:

3742148	Jun, 1973	Ledeen et al.	179/15.
3752932	Aug, 1973	Frisone	179/15.
3755786	Aug, 1973	Dixon et al.	179/15.
3755789	Aug, 1973	Collins	179/15.
3757050	Sep, 1973	Mizote	179/15.

Other Refs:
Primary Examiner: Springborn, Harvey E.
Assistant Examiner: Sachs, Michael C.
Attorney: McFarland; Philip J., Pannone; Joseph D.