Title: Binary parallel adder employing high speed gating circuitry

Abstract: In a binary parallel complementing L.S.I. adder, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage. The gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed, whereby very fast passage of a carry through the stages is achieved. The transmission gate consists of p- and n- channel MOS transistors with their sources connected in common to the input and their drain electrodes likewise connected in common to the output.

Do you think this is a good invention? Vote now:

Votes so far: For:(0) Against:(0)
Other info:

Inventors: Parsons, Brian Jeremy (Stevenage, EN)

Application Number: 449461
Filing Date: 1974-03-08
Publication_date: 1976-01-13
Assignee: Hawker Siddeley Dynamics Limited (EN)
Primary Class(es): 708/707 708/190, 708/703
Other Classes:
US Patent Ref:

3717755	Feb, 1973	Briley	235/175.
3743824	Jul, 1973	Smith	235/175.
3829713	Aug, 1974	Canning	307/251.
3843876	Oct, 1974	Fette et al.	235/175.

Other Refs:
Primary Examiner: Malzahn, David H.
Assistant Examiner:
Attorney: Rose & Edell