Title: Overlapped signal transition counter

Abstract: A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.

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Inventors: Check, Glenn P. (Rochester, MN, US)
Dimmick, Roger F. (Rochester, MN, US)

Application Number: 533736
Filing Date: 1974-12-17
Publication_date: 1976-01-06
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Class(es): 377/43 318/603, 327/1, 327/18
Other Classes:
US Patent Ref:

3466517	Sep, 1969	Leenhouts	318/603.
3671876	Jun, 1972	Oshiro	307/216.
3697779	Oct, 1972	Gee	307/216.

Other Refs:
Primary Examiner: Zazworsky, John
Assistant Examiner:
Attorney: Voss; Donald F.