Title: Method for manufacturing integrated circuits

Abstract: A method for manufacturing integrated circuits, said method comprising the steps of: Providing a first set of conductive zones on each of these portions of a substrate where electrical contacts are to be made, after having suitably doped said substrate with semiconductive material, Providing a selective insulating layer, so that the upper portions of said conductive zones be flush with the surface of said selective insulating layer, and Providing thereabove a second set of conductive zones adapted to constitute intended connections between said upper portions. Said method can be applied to the manufacture of MOS transistors.

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Inventors: Lacour, Jacques (Grenoble, FR)
Montier, Michel (Meylan, FR)
Suat, Jean-Pierre (Echirolles, FR)

Application Number: 368460
Filing Date: 1973-06-08
Publication_date: 1976-01-06
Assignee: Commissariat a l'Energie Atomique (Paris, FR)
Primary Class(es): 438/669 257/368, 257/410, 438/670, 438/701, 438/778, 438/783, 438/787
Other Classes:
US Patent Ref:

3341753	Sep, 1967	Cunningham et al.	317/234.
3495324	Feb, 1970	Guthrie et al.	29/578.
3602981	Sep, 1971	Kooi	29/580.
3641661	Feb, 1972	Canning et al.	29/578.
3667005	May, 1972	Cunningham et al.	317/234.
3700508	Oct, 1972	Keen	317/234.

Other Refs:
Primary Examiner: Lake, Roy
Assistant Examiner: Feinberg, Craig R.
Attorney: Cameron, Kerkam, Sutton, Stowell & Stowell